Advance circuit design techniques have resulted in increasingly complex circuits, both at the integrated circuit and printed circuit board level of electronic design. Diminished physical access is an unfortunate consequence of denser designs and shrinking interconnect pitch. Testability is needed, so that the finished product is still both controllable and observable during test and debug. Any manufacturing defect is preferably detectable during final test before product is shipped. This basic necessity is difficult to achieve for complex designs without taking testability into account in the logic design phase, so that automatic test equipment can test the product. Exemplary test architectures are disclosed in U.S. Pat. Nos. 5,056,093 and 5,054,024, to Whetsel, both filed Aug. 9, 1989, and the entire issue of the Texas Instruments Technical Journal, Vol. 5, No. 4, all of which are incorporated by reference herein.
Some existing test bus interfaces allow serial data to be shifted in and out of integrated circuits to facilitate testing of the logic in the device. These buses are designed primarily to transfer a single pattern of serial data into a selected scan path of the integrated circuit once per shift operation. However, in some applications, it may be required to utilize a serial test bus to load or unload a local memory in the integrated circuit. Since memories contain multiple data storage locations, multiple data patterns must be input using multiple shift operations. As a result, transferring data patterns into or out of memory is extremely time consuming due to the multiple shift operations.
Therefore, a need has arisen in the industry for a serial data input and output method which allows devices to be accessed in a more efficient manner than previously achieved.